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*Redundant

Figure 106.- Simplified functional block diagram of FDS.

Description

Timing and control block.- The timing and control block included the redundant oscillators, timing chains, and coded command decoding logic; the engineering sequencing and control logic; the science sequencing and control logic; and the power-on reset circuitry.

Engineering data block.- The circuits of the engineering data block performed digital and analog measurements that could be made at relatively low rates with no more than 7-bit accuracy. For the most part, the measurements consisted of the following four types:

External shift register: The subsystem being measured contained a register that was shifted out by the FDS.

Bilevel: The subsystem being measured sent a logic voltage level (either a 1 or a 0) that was sampled by the FDS.

Timer: The subsystem being measured sent a pulse that was used by the FDS to gate a signal of a known frequency into a counter.

Counter: The subsystem being measured sent pulses that incremented a counter in the FDS.

Analog engineering measurements consisted of the following four basic types:

Voltage measurements: The subsystem being measured sent a signal to the FDS in one of three voltage ranges: 0 to 100 mV, -1.5 to 1.5 V, and 0 to 3 V.

Strain-gage pressure measurements: The FDS produced signal levels of 12 and -12 V that excited a pressure sensor bridge in the subsystem being measured. The pressure sensors, in turn, sent back to the FDS the signal to be measured. This signal was conditioned-amplified and isolated. The signal level was from 0 to 3 V.

Potentiometric pressure and position measurements: The FDS sent a 3-V reference signal to the subsystem being measured. The 3-V reference appeared across a voltage divider whose ratio was related to pressure or to position. The output of the voltage divider was from 0 to 3 V.

Temperature measurements: The FDS generated a constant current of 1.0 mA that was sent to the temperature sensor in the subsystem to be measured. The temperature sensor produced an output voltage of 500 to 600 mV, which was measured across a sensor resistor divider network.

Accuracies of analog measurements, from the input to the FDS to the output of the ADC, were ±1 percent of full scale for all 0 to 3 V signals, +1 percent of full scale for all -1.5 to 1.5 V signals, ±3 percent of full scale for 0 to 100 mV signals, and ±3 percent of full scale for all 500 to 600 mV signals (temperature measurements). These accuracies were maintained under all specified environmental conditions encountered in the lifetime of the mission. The accuracy specifications did not include measurement error attributed to the nonzero source impedance of the voltage to be measured by the FDS. Input impedance of the analog measurement circuits of the FDS was greater than 1 mQ. Since the source impedance was maintained by the subsystem being measured, the associated error was not regulated by the FDS. However, the effect of this error was minimized through measurement calibration during spacecraft assembly. Each engineering analog measurement was converted into a 7-bit digital word for a range of 0 to 127 DN. Therefore, each word had a maximum resolution of 1/127 (0.787 percent). Zero DN corresponded to the most negative value for each of the 4 voltage ranges. At 0.5 DN equivalent input voltage, the FDS output changed from 0 to 1 DN.

Each of the two analog commutators, A and B, provided a programmable link between the many channels of analog data and the analog-to-digital converters. With the 8-bit commutator register, 256 locations were possible. Of these 256 locations, 32 were used for digital information, leaving 224 analog locations. These analog locations were divided between two identical analog commutators that operated independently for redundancy.

Infrared science data block.- The IRS multiplexers assembled the IRS format. Two identical redundant outputs were generated by separate FDS hardware to be bit-interleaved with 1000 bps engineering data (or all l's) and transmitted to DSS and MDS and also to be embedded into the VIS ID (TV flyback) data. Most of the IRS format was buffered in FDS memory and was generated, already multiplexed, by reading the memory at appropriate times. The IRS format was produced in 56 5-bit bytes. Forty-five of these bytes were read from memory, where each was a separate memory word: 10 bytes originate in hardware; 1 byte is spare. The A/PW data sources - MAWDS, VIS A and B, and IRTMS - were interlaced in time to enable all four of them to be counted in the same hardware. Two redundant counters were used, one associated with each memory and hence with each multiplexer. VIS and IRTMS A/PW converters processed bipolar data. The counters were implemented to produce sign-and-magnitude outputs. A total of 10 bits was allocated. The sign bit was developed by a polarity latch, and 9 bits of data were taken from the counter proper. A clock rate of 528 kHz was used to scale the data into a 9-bit number. A counter latched at nine l's to prevent overflow ambiguity for off-scale measurements. MAWDS A/PW handled unipolar data only. All 10 output bits were used for magnitude and came from the counter. A clock rate of 1.056 mHz was used to scale the data into a 10-bit number. The counter latched at ten l's to prevent overflow ambiguity. It latched at all 0's when the incoming data were zero or negative. The gated A/PW count clock was routed to the MAWDS integrator of the MAWDS sequence and control logic circuits. The low-rate engineering data were embedded into the science format. Engineering data A were embedded in science data A and engineering data B in science data B. Additionally, the required FDS status information to identify the number of new bits was also included. The engineering data (8 1/3 and 33 1/3 bps) resulted in either 2/3 or 9/10 data bits in each IRS minor frame. The engineering data bits were counted in a 1-bit counter, and the resulting parity bit was included as part of the FDS data rate in the FDS status word. FDS, MAWDS, and IRTMS digital words were obtained from various bits originating within the subsystem or the FDS control logic and were multiplexed into the IRS formats. The FDS status word was multiplexed redundantly, A into IRS mux A, and B into IRS mux B. MAWDS and IRTMS digital data were nonredundant, and therefore each status bit was routed to both multiplexers. The high-rate data outputs were controlled by the high-rate gating and control circuitry. The 1000-bps IRS data and the 1000-bps engineering data were bit-interleaved to produce 2000-bps high-rate data. When the engineering data rate was 8 1/3 or 33 1/3 bps, the 1000-bps engineering data consisted of all l's. The control information for the output of the high-rate multiplexer was contained in the data rate bits of the coded command of the engineering data control CCS.

Visual imaging data block.- The visual imaging data block received 2.112-mHz data from the VIS ADC. It processed these data from serial format to seven tracks of parallel data suitable for recording on the DTR. The logic circuit that performed this function consisted mainly of steering logic and rate buffering and is referred to herein as the VIS processor. Processed data on the seven tracks to the DSS occurred at a rate of 301 714 2/7 bps (per track). A single VIS line format required 4 8/33 msec to send and contained 1280 bits. Except for track ID, the first 76 bits of the format for a given VIS line were the same for all seven tracks. Bits 77 through 1280 on each track were the binary values for 172 7-bit pixels, MSB first. Each VIS line contained 1204 pixels, one-seventh of which went on each of the seven tracks to each DTR. The two sets of outputs to the two DTR's were identical and redundant. VIS data were received from each camera ADC simultaneously and continuously. Since the cameras were used alternately, only one of these data streams was processed; the other was discarded. Two identical processors handled the VIS data redundantly. Processor A furnished seven tracks of output data for DTR A; processor B served DTR B.

Memory block.- The memory block encompassed two identical plated-wire memories and two associated memory controllers. Each memory provided random access storage and retrieval of 1024 words of digital data, for a total of 2048 words of 8 bits each. The memories were mounted on a common subchassis but were otherwise completely separate and independent. The memories operated in complete synchronism. Each memory included the plated-wire mats and all associated electronics but excluded power conversion and power conditioning. Address bits and data to and from either memory were transferred in parallel. The memories were interrogated without destroying the stored data. Stored data did not change as a result of power interruptions. Normal operation of the memory was inhibited by internal circuitry when any of the supply voltages were outside of predetermined tolerance limits, approximately +6 to +8 percent. If this condition occurred during a read or write cycle, the memory completed the cycle properly.

Power conversion block.- The power conversion block included two identical power converters, each of which converted the 2.4-kHz input power to the specific voltages required to operate the FDS circuits, logic, relays, and memories. The power converter function also included relay switching for the outputs of the power converters. The two power converters were used as a redundant set where one was active and the other was standby redundant. Switching of the power input from one converter to the other was controlled by the power subsystem to guarantee that only one power converter was on at any one time and when power was switched off then on again, the power converter last used came back on.

Data Modes, Rates, and Formats

The FDS supplies data to the TMU of the MDS over two pairs of transmission lines. One pair furnished low-rate data, while the other pair supplied high-

rate data. The low-rate data were also supplied to the CCS via a single line to both CCS processors. High-rate data and VIS data were also supplied to the DSS for recording.

Orbiter time.- The fundamental interval in the FDS was the 280-msec period for IRS data minor frame. The count of these 280-msec periods was called VO time. The IRS data format contained a 30-bit VO time word. The length of this word allowed a maximum counting time of 3479.9 days (approximately 116 mo) before repeating. The 30-bit VO time word was contained in both FDS nondestructive memories and could be reprogrammed to any desired count.

Engineering data.- Figure 107 illustrates the basic engineering format structure which was used for all four rates (engineering A at 1000 bps, engineering B at 33 1/3 bps, engineering C at 8 1/3 bps, and engineering D at 8 1/3 bps) and for all five engineering formats (AI (launch), All (cruise), BI (maneuver), and BII (orbit) programmable formats and a fixed format). Each word in the format was 7 bits long and was read out MSB first. A minor frame (from sync word to sync word) was 32 words long. A major frame was defined as one pass through the 400 deck. At the completion of a major data frame, each 400 deck position had been sampled 1 time; each 300 deck, 2 times; each 200 deck, 16 times; and each 100 deck, 128 times. Because of cummutation limitations, less than the total number of measurements could be commutated at any one time for a given format. Table 33 gives the sampling intervals for each rate.

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